1 radiation hardened quad voltage comparator hs-139rh, hs-139eh the radiation hardened hs-139rh, hs-139eh consists of four independent single or dual su pply voltage comparators on a single monolithic substrate. the common mode input voltage range includes ground, even when operated from a single supply and the low supply current makes these comparators suitable for low power applications. these types were designed to directly interface with ttl and cmos. the hs-139rh, hs-139eh is fabric ated on our dielectrically isolated rad hard silicon gate (rsg) process, which provides an immunity to single event latch-up and the capability of highly reliable performance in any radiation environment. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbers listed below must be used when ordering. detailed electrical specificatio ns for the hs-139rh, hs-139eh are contained in smd 5962-98613 . a ?hot-link? is provided on our homepage with instructions for downloading. www.intersil.com/spacedefense/newsafclasst.asp features ? qml qualified per mil-prf-38535 requirements ? radiation environment - latch-up free under any conditions - total dose (max). . . . . . . . . . . . . . . . . . . . . . 3 x 10 5 rad(si) - seu let threshold . . . . . . . . . . . . . . . . . . . 20mev/cm 2 /mg - low dose rate effects immunity ? 100v output voltage withstand capability ? esd protection to >3000v ? differential input voltage range equal to the supply voltage ? input offset voltage (v io ) . . . . . . . . . . . . . . . . . . . . 2mv (max) ? quiescent supply current . . . . . . . . . . . . . . . . . . . . 2ma (max) ? pb-free (rohs compliant) applications ?pulse generators ? timing circuitry ? level shifting ? analog-to-digital conversion ordering information ordering number (note) internal mkt. number part marking temp. range (c) package (rohs compliant) package drawing number 5962f9861303vcc HS1-139EH-Q q 5962f98 61303vcc -55 to +125 14 ld sbdip d14.3 5962f9861301vcc hs1-139rh-q q 5962f98 61301vcc -55 to +125 14 ld sbdip d14.3 5962f9861301qcc hs1-139rh-8 q 5962f98 61301qcc -55 to +125 14 ld sbdip d14.3 hs1-139rh/proto hs1-139rh/proto hs1-139rh/proto -55 to +125 14 ld sbdip d14.3 5962f9861301vxc hs9-139rh-q q 5962f98 61301vxc -55 to +125 14 ld flatpack k14.a 5962f9861301qxc hs9-139rh-8 q 5962f98 61301qxc -55 to +125 14 ld flatpack k14.a 5962f9861302vxc hs9-139eh-q q 5962f98 61302vxc -55 to +125 14 ld flatpack k14.a hs9-139rh/proto hs9-139rh/proto hs9-139rh /proto -55 to +125 14 ld flatpack k14.a note: these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 1999, 2004, 2008, 2009, 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. july 12, 2012 fn3573.5
hs-139rh, hs-139eh 2 fn3573.5 july 12, 2012 pin configurations s hs-139rh, hs-139eh (sbdip cdip2-t14) top view hs-139rh, hs-139eh (flatpack cdfp3-f14) top view die characteristics die dimensions: 3750m x 2820m (148 mils x 111 mils) 483m 25.4m (19 mils 1 mil) interface materials: glassivation: type: silox (sio 2 ) thickness: 8.0k? 1.0k? top metallization: type: alsicu thickness: 16.0k? 2k? substrate: radiation hardened silicon gate, dielectric isolation backside finish: silicon assembly related information: substrate potential: unbiased (di) additional information: worst case current density: <2.0 x 10 5 a/cm 2 transistor count: 49 out 2 out 1 v+ - in 1 + in 1 - in 2 + in 2 out 3 out 4 gnd + in 4 - in 4 + in 3 - in 3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14 13 12 11 10 9 8 2 3 4 5 6 7 1 out 2 out 1 v+ - in 1 + in 1 - in 2 +in 2 out 3 out 4 gnd + in 4 - in 4 + in 3 - in 3
hs-139rh, hs-139eh 3 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn3573.5 july 12, 2012 for additional products, see www.intersil.com/product_tree metallization mask layout hs-139rh, hs-139eh gnd +in4 -in4 v+ -in1 +in1 +in3 -in3 +in2 -in2 out4 out3 out2 out1 (9) (8) (7) (6) (5) (4) (3) (2) (1) (14) (13) (12) (11) (10) table 1. hs-139rh, hs-139eh pad coordinates relative to pin 1 pin number pad name x coordinates y coordinates 1 out 2 0 0 2 out 1 0 -535 3 v+ 1323 -688 4 -in 1 1862 -670 5 +in 1 2439 -670 6 -in 2 3084 -299 7 +in 2 3084 278 8 -in 3 3084 518 9 +in 3 3084 1095 10 -in 4 2439 1466 11 +in 4 1862 1466 12 gnd 1550 1503 13 out 4 0 1331 14 out 3 0 796 note: dimensions in microns
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